1 //  2 // (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.  3 //  4 //                                                                   5 // This file contains confidential and proprietary information  6 // of Xilinx, Inc. and is protected under U.S. and  7 // international copyright and other intellectual property  8 // laws.  9 //  10 // DISCLAIMER 11 // This disclaimer is not a license and does not grant any 12 // rights to the materials distributed herewith. Except as 13 // otherwise provided in a valid license issued to you by 14 // Xilinx, and to the maximum extent permitted by applicable 15 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 // (2) Xilinx shall not be liable (whether in contract or tort, 21 // including negligence, or under any other theory of 22 // liability) for any loss or damage of any kind or nature 23 // related to, arising under or in connection with these 24 // materials, including for any direct, or any indirect, 25 // special, incidental, or consequential loss or damage 26 // (including loss of data, profits, goodwill, or any type of 27 // loss or damage suffered as a result of any action brought 28 // by a third party) even if such damage or loss was 29 // reasonably foreseeable or Xilinx had been advised of the 30 // possibility of the same. 31 //  32 // CRITICAL APPLICATIONS 33 // Xilinx products are not designed or intended to be fail- 34 // safe, or for use in any application requiring fail-safe 35 // performance, such as life-support or safety devices or 36 // systems, Class III medical devices, nuclear facilities, 37 // applications related to the deployment of airbags, or any 38 // other applications that could lead to death, personal 39 // injury, or severe property or environmental damage 40 // (individually and collectively, "Critical 41 // Applications"). Customer assumes the sole risk and 42 // liability of any use of Xilinx products in Critical 43 // Applications, subject only to applicable laws and 44 // regulations governing limitations on product liability. 45 //  46 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 //     PART OF THIS FILE AT ALL TIMES.                                 48 `timescale 1ps/1ps 49 (* DowngradeIPIdentifiedWarnings = "yes" *) 50  51  52 module srio_example_top_srio_gen2_0 #( 53     parameter SIM_VERBOSE               = 1, // If set, generates unsynthesizable reporting 54     parameter VALIDATION_FEATURES       = 1, // If set, uses internal instruction sequences for hw and sim test 55     parameter QUICK_STARTUP             = 1, // If set, quick-launch configuration access is contained here 56     parameter STATISTICS_GATHERING      = 1, // If set, I/O can be rerouted to the maint port [0,1] 57     parameter C_LINK_WIDTH              = 1 58     ) 59    //  port declarations ---------------- 60    ( 61     // Clocks and Resets 62     input            sys_clkp,              // MMCM reference clock 63     input            sys_clkn,              // MMCM reference clock 64  65     input            sys_rst,               // Global reset signal 66  67     // high-speed IO 68     input           srio_rxn0,              // Serial Receive Data 69     input           srio_rxp0,              // Serial Receive Data 70  71  72  73     output          srio_txn0,              // Serial Transmit Data 74     output          srio_txp0,              // Serial Transmit Data 75  76  77  78     input           sim_train_en,           // Set this only when simulating to reduce the size of counters 79     output  [7:0]   led0 80  81    ); 82    //  ---------------------------------- 83  84  85   // wire declarations ---------------- 86 // 87 // ----------------------------------------------------------------------------- 88 // Note : Below portion of the wire declaration should be commented when 89 //        used in non-shared mode AND the SRIO core 2nd instance is used to share 90 //        common logic like clk, rst and GT Common with another instance of SRIO 91 //        with Shared Logic (in DUT) option if the simulator throws errors. 92 // ----------------------------------------------------------------------------- 93     wire            log_clk; 94     wire            phy_clk; 95     wire            gt_pcs_clk; 96     wire            log_rst; 97     wire            phy_rst; 98     wire            clk_lock;               // asserts from the MMCM 99 //100 101     // signals into the DUT102 103 104     wire            ireq_tvalid;105     wire            ireq_tready;106     wire            ireq_tlast;107     wire   [63:0]   ireq_tdata;108     wire   [7:0]    ireq_tkeep;109     wire   [31:0]   ireq_tuser;110 111     wire            iresp_tvalid;112     wire            iresp_tready;113     wire            iresp_tlast;114     wire    [63:0]  iresp_tdata;115     wire    [7:0]   iresp_tkeep;116     wire    [31:0]  iresp_tuser;117 118     wire            treq_tvalid;119     wire            treq_tready;120     wire            treq_tlast;121     wire    [63:0]  treq_tdata;122     wire    [7:0]   treq_tkeep;123     wire    [31:0]  treq_tuser;124 125     wire            tresp_tvalid;126     wire            tresp_tready;127     wire            tresp_tlast;128     wire   [63:0]   tresp_tdata;129     wire   [7:0]    tresp_tkeep;130     wire   [31:0]   tresp_tuser;131 132     wire            maintr_rst = 1'b0;133 134     wire            maintr_awvalid;135     wire            maintr_awready;136     wire   [31:0]   maintr_awaddr;137     wire            maintr_wvalid;138     wire            maintr_wready;139     wire   [31:0]   maintr_wdata;140     wire            maintr_bvalid;141     wire            maintr_bready;142     wire   [1:0]    maintr_bresp;143 144     wire            maintr_arvalid;145     wire            maintr_arready;146     wire   [31:0]   maintr_araddr;147     wire            maintr_rvalid;148     wire            maintr_rready;149     wire   [31:0]   maintr_rdata;150     wire   [1:0]    maintr_rresp;151 152     // signals from Validation modules153     wire            val_ireq_tvalid;154     wire            val_ireq_tready;155     wire            val_ireq_tlast;156     wire   [63:0]   val_ireq_tdata;157     wire   [7:0]    val_ireq_tkeep;158     wire   [31:0]   val_ireq_tuser;159 160     wire            val_iresp_tvalid;161     wire            val_iresp_tready;162     wire            val_iresp_tlast;163     wire    [63:0]  val_iresp_tdata;164     wire    [7:0]   val_iresp_tkeep;165     wire    [31:0]  val_iresp_tuser;166 167     wire            val_treq_tvalid;168     wire            val_treq_tready;169     wire            val_treq_tlast;170     wire    [63:0]  val_treq_tdata;171     wire    [7:0]   val_treq_tkeep;172     wire    [31:0]  val_treq_tuser;173 174     wire            val_tresp_tvalid;175     wire            val_tresp_tready;176     wire            val_tresp_tlast;177     wire   [63:0]   val_tresp_tdata;178     wire   [7:0]    val_tresp_tkeep;179     wire   [31:0]   val_tresp_tuser;180 181     wire            val_maintr_awvalid;182     wire            val_maintr_awready;183     wire   [31:0]   val_maintr_awaddr;184     wire            val_maintr_wvalid;185     wire            val_maintr_wready;186     wire   [31:0]   val_maintr_wdata;187     wire            val_maintr_bvalid;188     wire            val_maintr_bready;189     wire   [1:0]    val_maintr_bresp;190 191     wire            val_maintr_arvalid;192     wire            val_maintr_arready;193     wire   [31:0]   val_maintr_araddr;194     wire            val_maintr_rvalid;195     wire            val_maintr_rready;196     wire   [31:0]   val_maintr_rdata;197     wire   [1:0]    val_maintr_rresp;198 199 200 //--201 //----------------------------------------------------------------------------//202 203 204 //--205 206     // other core output signals that may be used by the user207     wire     [23:0] port_timeout;           // Timeout value user can use to detect a lost packet208     wire            phy_rcvd_mce;           // MCE control symbol received209     (* mark_debug = "true" *)210     wire            phy_rcvd_link_reset;    // Received 4 consecutive reset symbols211     wire            port_error;             // In Port Error State212     //(* mark_debug = "true" *)// this constraint is commented as it is failing due to new MLO flow213     wire            mode_1x;                // Link is trained down to 1x mode214     wire            srio_host;              // Endpoint is the system host215     wire    [223:0] phy_debug;              // Useful debug signals216     217     wire            gtrx_disperr_or;        // GT disparity error (reduce ORed)218     219     wire            gtrx_notintable_or;     // GT not in table error (reduce ORed)220     wire     [15:0] deviceid;               // Device ID221     wire            port_decode_error;      // No valid output port for the RX transaction222     (* mark_debug = "true" *)223     wire            idle_selected;          // The IDLE sequence has been selected224     (* mark_debug = "true" *)225     wire            idle2_selected;         // The PHY is operating in IDLE2 mode226     wire            autocheck_error;        // when set, packet didn't match expected227     (* mark_debug = "true" *)228     wire            port_initialized;       // Port is Initialized229     (* mark_debug = "true" *)230     wire            link_initialized;       // Link is Initialized231     wire            exercise_done;          // sets when the generator(s) has completed232 233     // other core output signals that may be used by the user234     wire            phy_mce = 1'b0;         // Send MCE control symbol235     wire            phy_link_reset = 1'b0;  // Send link reset control symbols236     wire            force_reinit = 1'b0;    // Force reinitialization237 238 239     // convert to ports when not using the pattern generator240 241 242     wire            axis_ireq_tvalid;243     wire            axis_ireq_tready;244     wire            axis_ireq_tlast;245     wire   [63:0]   axis_ireq_tdata;246     wire   [7:0]    axis_ireq_tkeep;247     wire   [31:0]   axis_ireq_tuser;248 249     wire            axis_iresp_tvalid;250     wire            axis_iresp_tready;251     wire            axis_iresp_tlast;252     wire    [63:0]  axis_iresp_tdata;253     wire    [7:0]   axis_iresp_tkeep;254     wire    [31:0]  axis_iresp_tuser;255 256     wire            axis_treq_tvalid;257     wire            axis_treq_tready;258     wire            axis_treq_tlast;259     wire    [63:0]  axis_treq_tdata;260     wire    [7:0]   axis_treq_tkeep;261     wire    [31:0]  axis_treq_tuser;262 263     wire            axis_tresp_tvalid;264     wire            axis_tresp_tready;265     wire            axis_tresp_tlast;266     wire   [63:0]   axis_tresp_tdata;267     wire   [7:0]    axis_tresp_tkeep;268     wire   [31:0]   axis_tresp_tuser;269 270     wire            axis_maintr_rst = 1'b0;271     wire            axis_maintr_awvalid = 1'b0;272     wire            axis_maintr_awready;273     wire   [31:0]   axis_maintr_awaddr = 1'b0;274     wire            axis_maintr_wvalid = 1'b0;275     wire            axis_maintr_wready;276     wire   [31:0]   axis_maintr_wdata = 1'b0;277     wire   [3:0]    axis_maintr_wstrb = 1'b0;278     wire            axis_maintr_bvalid;279     wire            axis_maintr_bready = 1'b0;280     wire   [1:0]    axis_maintr_bresp;281 282     wire            axis_maintr_arvalid = 1'b0;283     wire            axis_maintr_arready;284     wire   [31:0]   axis_maintr_araddr = 1'b0;285     wire            axis_maintr_rvalid;286     wire            axis_maintr_rready = 1'b0;287     wire   [31:0]   axis_maintr_rdata;288     wire   [1:0]    axis_maintr_rresp;289 290     wire            ireq_autocheck_error;291     wire            ireq_request_done;292     wire            maint_autocheck_error;293     wire            maint_done;294 295     // Vivado debug outputs for control of296     (* mark_debug = "true" *)297     wire            peek_poke_go;298     (* mark_debug = "true" *)299     wire [23:0]     user_addr;300     (* mark_debug = "true" *)301     wire  [3:0]     user_ftype;302     (* mark_debug = "true" *)303     wire  [3:0]     user_ttype;304     (* mark_debug = "true" *)305     wire  [7:0]     user_size;306     (* mark_debug = "true" *)307     wire [63:0]     user_data;308     (* mark_debug = "true" *)309     wire  [3:0]     user_hop;310     (* mark_debug = "true" *)311     wire [15:0]     dest_id;312     (* mark_debug = "true" *)313     wire [15:0]     source_id;314     (* mark_debug = "true" *)315     wire            id_override;316     (* mark_debug = "true" *)317     wire            register_reset;318     (* mark_debug = "true" *)319     wire            reset_all_registers;320     (* mark_debug = "true" *)321     wire  [3:0]     stats_address;322     //(* mark_debug = "true" *)323     // wire            send_pna;324     // (* mark_debug = "true" *)325     // wire  [2:0]     sent_pna_cause_lsb;326     // (* mark_debug = "true" *)327     // wire            in_recoverable_detect;328     // (* mark_debug = "true" *)329     // wire            in_retry_detect;330     // (* mark_debug = "true" *)331     // wire            out_recoverable_detect;332     // (* mark_debug = "true" *)333     // wire            out_fatal_detect;334     335     wire       core_sent_pna;336     337     wire       core_received_pna;338     339     wire       core_sent_pr;340     341     wire       core_received_pr;342 343     // Debug signals344     wire            go_req   = peek_poke_go && user_ftype != 4'h8;345     wire            go_maint = peek_poke_go && user_ftype == 4'h8;346     wire            maint_inst = user_ttype == 4'h0;347     reg   [63:0]    captured_data;348     (* mark_debug = "true" *)349     wire            continuous_go;350     reg             continuous_go_q;351     reg             ireq_autocheck_error_q;352     reg             ireq_request_done_q;353     reg             reset_request_gen;354     (* mark_debug = "true" *)355     reg             continuous_in_process;356     reg             reset_continuous_set;357     (* mark_debug = "true" *)358     reg             stop_continuous_test;359     reg   [15:0]    reset_continuous_srl;360     wire  [31:0]    stats_data;361   // }}} End wire declarations ------------362 363 364   // {   {   { Drive LEDs to Development Board -------365     assign led0[0] = 1'b1;366     assign led0[1] = 1'b1;367     assign led0[2] = !mode_1x;368     assign led0[3] = port_initialized;369     assign led0[4] = link_initialized;370     assign led0[5] = clk_lock;371     assign led0[6] = sim_train_en ? autocheck_error : 1'b0;372     assign led0[7] = sim_train_en ? exercise_done : 1'b0;373   // }}} End LEDs to Development Board ---------374 375     // assign send_pna               = phy_debug[0];376     // assign sent_pna_cause_lsb     = phy_debug[34:32];377     // assign in_recoverable_detect  = phy_debug[40];378     // assign in_retry_detect        = phy_debug[39];379     // assign out_recoverable_detect = phy_debug[38];380     // assign out_fatal_detect       = phy_debug[37];381     // assign send_pna               = phy_debug[0];382     assign core_sent_pna     = phy_debug[160];383     assign core_received_pna = phy_debug[161];384     assign core_sent_pr      = phy_debug[162];385     assign core_received_pr  = phy_debug[163];386 387 388 389 390       assign continuous_go        = 1'b0;391       assign peek_poke_go         = 1'b0;392       assign user_addr            = 24'b0;393       assign user_ftype           = 4'b0;394       assign user_ttype           = 4'b0;395       assign user_size            = 8'b0;396       assign user_data            = 64'b0;397       assign user_hop             = 4'b0;398       assign dest_id              = 16'b0;399       assign source_id            = 16'b0;400       assign id_override          = 1'b0;401       assign register_reset       = 1'b0;402       assign reset_all_registers  = 1'b0;403       assign stats_address        = 4'b0;404 405 406 407 408   // feed back the last captured data to VIO409   always @(posedge log_clk) begin410     if (log_rst) begin411       captured_data <= 64'h0;412     // IO interface413     end else if (iresp_tvalid && iresp_tready) begin414       captured_data <= axis_iresp_tdata;415     // maintenance interface416     end else if (maintr_rvalid && maintr_rready) begin417       captured_data <= axis_maintr_rdata;418     end419   end420 421   // Continuous data flow422   always @(posedge log_clk) begin423     continuous_go_q        <= continuous_go;424     ireq_request_done_q    <= ireq_request_done;425     ireq_autocheck_error_q <= ireq_autocheck_error;426     reset_request_gen      <= sim_train_en ? log_rst : |reset_continuous_srl && continuous_in_process;427   end428 429   always @(posedge log_clk) begin430     if (log_rst) begin431       continuous_in_process <= 1'b0;432     end else if (continuous_go && !continuous_go_q) begin433       continuous_in_process <= 1'b1;434     end else if (!continuous_go && continuous_go_q) begin435       continuous_in_process <= 1'b0;436     end437   end438   always @(posedge log_clk) begin439     if (log_rst) begin440       reset_continuous_set <= 1'b0;441       stop_continuous_test <= 1'b0;442     end else if (continuous_go && !continuous_go_q) begin443       reset_continuous_set <= 1'b1;444       stop_continuous_test <= 1'b0;445     end else if (!ireq_autocheck_error_q && ireq_autocheck_error && continuous_in_process) begin446       stop_continuous_test <= 1'b1;447     end else if (!stop_continuous_test && !ireq_request_done_q && ireq_request_done &&448                   continuous_in_process) begin449       reset_continuous_set <= 1'b1;450     end else begin451       reset_continuous_set <= 1'b0;452     end453   end454   always @(posedge log_clk) begin455     if (log_rst) begin456       reset_continuous_srl <= 16'h0;457     end else if (reset_continuous_set) begin458       reset_continuous_srl <= 16'hFFFF;459     end else begin460       reset_continuous_srl <= {reset_continuous_srl[14:0], 1'b0};461     end462   end463 464   // SRIO_DUT instantation -----------------465   // for production and shared logic in the core466   srio_gen2_0  srio_gen2_0_inst467      (//---------------------------------------------------------------468       .sys_clkp                (sys_clkp  ),469       .sys_clkn                (sys_clkn  ),470       .sys_rst                 (sys_rst   ),471       // all clocks as output in shared logic mode472       .log_clk_out             (log_clk   ),473       .phy_clk_out             (phy_clk   ),474       .gt_clk_out              (gt_clk    ),475       .gt_pcs_clk_out          (gt_pcs_clk),476 477       .drpclk_out              (drpclk    ),478 479       .refclk_out              (refclk    ),480 481       .clk_lock_out            (clk_lock  ),482       // all resets as output in shared logic mode483       .log_rst_out             (log_rst   ),484       .phy_rst_out             (phy_rst   ),485       .buf_rst_out             (buf_rst   ),486       .cfg_rst_out             (cfg_rst   ),487       .gt_pcs_rst_out          (gt_pcs_rst),488 489 //---------------------------------------------------------------490 491       .gt0_qpll_clk_out           (gt0_qpll_clk_out       ),492       .gt0_qpll_out_refclk_out    (gt0_qpll_out_refclk_out),493 494 495 496 // //---------------------------------------------------------------497       .srio_rxn0               (srio_rxn0),498       .srio_rxp0               (srio_rxp0),499 500       .srio_txn0               (srio_txn0),501       .srio_txp0               (srio_txp0),502 503       .s_axis_ireq_tvalid            (ireq_tvalid),504       .s_axis_ireq_tready            (ireq_tready),505       .s_axis_ireq_tlast             (ireq_tlast),506       .s_axis_ireq_tdata             (ireq_tdata),507       .s_axis_ireq_tkeep             (ireq_tkeep),508       .s_axis_ireq_tuser             (ireq_tuser),509 510       .m_axis_iresp_tvalid           (iresp_tvalid),511       .m_axis_iresp_tready           (iresp_tready),512       .m_axis_iresp_tlast            (iresp_tlast),513       .m_axis_iresp_tdata            (iresp_tdata),514       .m_axis_iresp_tkeep            (iresp_tkeep),515       .m_axis_iresp_tuser            (iresp_tuser),516 517       .s_axis_tresp_tvalid           (tresp_tvalid),518       .s_axis_tresp_tready           (tresp_tready),519       .s_axis_tresp_tlast            (tresp_tlast),520       .s_axis_tresp_tdata            (tresp_tdata),521       .s_axis_tresp_tkeep            (tresp_tkeep),522       .s_axis_tresp_tuser            (tresp_tuser),523 524       .m_axis_treq_tvalid            (treq_tvalid),525       .m_axis_treq_tready            (treq_tready),526       .m_axis_treq_tlast             (treq_tlast),527       .m_axis_treq_tdata             (treq_tdata),528       .m_axis_treq_tkeep             (treq_tkeep),529       .m_axis_treq_tuser             (treq_tuser),530 531       .s_axi_maintr_rst              (maintr_rst),532 533       .s_axi_maintr_awvalid          (maintr_awvalid),534       .s_axi_maintr_awready          (maintr_awready),535       .s_axi_maintr_awaddr           (maintr_awaddr),536       .s_axi_maintr_wvalid           (maintr_wvalid),537       .s_axi_maintr_wready           (maintr_wready),538       .s_axi_maintr_wdata            (maintr_wdata),539       .s_axi_maintr_bvalid           (maintr_bvalid),540       .s_axi_maintr_bready           (maintr_bready),541       .s_axi_maintr_bresp            (maintr_bresp),542 543       .s_axi_maintr_arvalid          (maintr_arvalid),544       .s_axi_maintr_arready          (maintr_arready),545       .s_axi_maintr_araddr           (maintr_araddr),546       .s_axi_maintr_rvalid           (maintr_rvalid),547       .s_axi_maintr_rready           (maintr_rready),548       .s_axi_maintr_rdata            (maintr_rdata),549       .s_axi_maintr_rresp            (maintr_rresp),550 551       .sim_train_en                  (sim_train_en),552       .phy_mce                       (phy_mce),553       .phy_link_reset                (phy_link_reset),554       .force_reinit                  (force_reinit),555 556 557       .phy_rcvd_mce                  (phy_rcvd_mce       ),558       .phy_rcvd_link_reset           (phy_rcvd_link_reset),559       .phy_debug                     (phy_debug          ),560       .gtrx_disperr_or               (gtrx_disperr_or    ),561       .gtrx_notintable_or            (gtrx_notintable_or ),562 563       .port_error                    (port_error         ),564       .port_timeout                  (port_timeout       ),565       .srio_host                     (srio_host          ),566       .port_decode_error             (port_decode_error  ),567       .deviceid                      (deviceid           ),568       .idle2_selected                (idle2_selected     ),569       .phy_lcl_master_enable_out     (), // these are side band output only signals570       .buf_lcl_response_only_out     (),571       .buf_lcl_tx_flow_control_out   (),572       .buf_lcl_phy_buf_stat_out      (),573       .phy_lcl_phy_next_fm_out       (),574       .phy_lcl_phy_last_ack_out      (),575       .phy_lcl_phy_rewind_out        (),576       .phy_lcl_phy_rcvd_buf_stat_out (),577       .phy_lcl_maint_only_out        (),578 //---579 580 581 582 583 584 //---585       .port_initialized              (port_initialized  ),586       .link_initialized              (link_initialized  ),587       .idle_selected                 (idle_selected     ),588       .mode_1x                       (mode_1x           )589      );590   // End of SRIO_DUT instantiation ---------591 592 593   // Initiator-driven side --------------------594 595 596   // {   {   { IREQ Interface ---------------------------597   // Select between internally-driven sequences or user sequences598   assign ireq_tvalid = (VALIDATION_FEATURES) ? val_ireq_tvalid : axis_ireq_tvalid;599   assign ireq_tlast  = (VALIDATION_FEATURES) ? val_ireq_tlast  : axis_ireq_tlast;600   assign ireq_tdata  = (VALIDATION_FEATURES) ? val_ireq_tdata  : axis_ireq_tdata;601   assign ireq_tkeep  = (VALIDATION_FEATURES) ? val_ireq_tkeep  : axis_ireq_tkeep;602   assign ireq_tuser  = (VALIDATION_FEATURES) ? val_ireq_tuser  : axis_ireq_tuser;603 604   assign axis_ireq_tready = (!VALIDATION_FEATURES) && ireq_tready;605   assign val_ireq_tready  = (VALIDATION_FEATURES)  && ireq_tready;606 607 608 609 610   // When enabled, report results.611   // This is a simulation-only option and cannot be synthesized612   generate if (SIM_VERBOSE) begin: ireq_reporting_gen613    srio_report614      #(.VERBOSITY        (2),615        .DIRECTION        (1),616        .NAME             (0))  // Data is flowing into the core617      srio_ireq_report_inst618       (619       .log_clk                 (log_clk),620       .log_rst                 (log_rst),621 622       .tvalid                  (ireq_tvalid),623       .tready                  (ireq_tready),624       .tlast                   (ireq_tlast),625       .tdata                   (ireq_tdata),626       .tkeep                   (ireq_tkeep),627       .tuser                   (ireq_tuser)628      );629   end630   endgenerate631   // }}} End of IREQ Interface --------------------632 633 634   // {   {   { Initiator Generator/Checker --------------635 636   // If internally-driven sequences are required637   generate if (VALIDATION_FEATURES) begin: ireq_validation_gen638    srio_request_gen_srio_gen2_0639      #(.SEND_SWRITE       (1),640        .SEND_NWRITER      (1),641        .SEND_NWRITE       (1),642        .SEND_NREAD        (1),643        .SEND_FTYPE9       (0),644        .SEND_DB           (1),645        .SEND_MSG          (1))646      srio_request_gen_inst (647       .log_clk                 (log_clk),648       .log_rst                 (reset_request_gen),649 650       .deviceid                (deviceid),651       .dest_id                 (dest_id),652       .source_id               (source_id),653       .id_override             (id_override),654 655       .val_ireq_tvalid         (val_ireq_tvalid),656       .val_ireq_tready         (val_ireq_tready),657       .val_ireq_tlast          (val_ireq_tlast),658       .val_ireq_tdata          (val_ireq_tdata),659       .val_ireq_tkeep          (val_ireq_tkeep),660       .val_ireq_tuser          (val_ireq_tuser),661 662       .val_iresp_tvalid        (val_iresp_tvalid),663       .val_iresp_tready        (val_iresp_tready),664       .val_iresp_tlast         (val_iresp_tlast),665       .val_iresp_tdata         (val_iresp_tdata),666       .val_iresp_tkeep         (val_iresp_tkeep),667       .val_iresp_tuser         (val_iresp_tuser),668 669       .link_initialized        (link_initialized),670 671       // use these ports to peek/poke IO transactions672       .go                      (go_req),673       .user_addr               ({   10'h000, user_addr}),674       .user_ftype              (user_ftype),675       .user_ttype              (user_ttype),676       .user_size               (user_size),677       .user_data               (user_data),678 679       .request_autocheck_error (ireq_autocheck_error),680       .request_done            (ireq_request_done)681      );682   end683   endgenerate684   // }}} End of Initiator Generator/Checker -------685 686 687   // {   {   { IRESP Interface --------------------------688   // Select between internally-driven sequences or user sequences689 690   assign iresp_tready = (VALIDATION_FEATURES) ? val_iresp_tready : axis_iresp_tready;691 692   assign val_iresp_tvalid  = (VALIDATION_FEATURES) && iresp_tvalid;693   assign val_iresp_tlast   = iresp_tlast;694   assign val_iresp_tdata   = iresp_tdata;695   assign val_iresp_tkeep   = iresp_tkeep;696   assign val_iresp_tuser   = iresp_tuser;697 698   assign axis_iresp_tvalid = (!VALIDATION_FEATURES) && iresp_tvalid;699   assign axis_iresp_tlast  = iresp_tlast;700   assign axis_iresp_tdata  = iresp_tdata;701   assign axis_iresp_tkeep  = iresp_tkeep;702   assign axis_iresp_tuser  = iresp_tuser;703 704 705   // When enabled, report results.706   // This is a simulation-only option and cannot be synthesized707   generate if (SIM_VERBOSE) begin: iresp_reporting_gen708    srio_report709      #(.VERBOSITY              (2),710        .DIRECTION              (0),711        .NAME                   (1))  // Data is flowing out of the core712      srio_iresp_report_inst713       (714       .log_clk                 (log_clk),715       .log_rst                 (log_rst),716 717       .tvalid                  (iresp_tvalid),718       .tready                  (iresp_tready),719       .tlast                   (iresp_tlast),720       .tdata                   (iresp_tdata),721       .tkeep                   (iresp_tkeep),722       .tuser                   (iresp_tuser)723      );724   end725   endgenerate726   // }}} End of IRESP Interface -------------------727 728 729 730 731 732   assign autocheck_error         = ireq_autocheck_error || maint_autocheck_error;733   assign exercise_done           = ireq_request_done && maint_done;734 735   // }}} End of Initiator-driven side -------------736 737 738   // {   {   { Target-driven side -----------------------739 740   // {   {   { TRESP Interface --------------------------741   // Select between internally-driven sequences or user sequences742   assign tresp_tvalid = (VALIDATION_FEATURES) ? val_tresp_tvalid : axis_tresp_tvalid;743   assign tresp_tlast  = (VALIDATION_FEATURES) ? val_tresp_tlast  : axis_tresp_tlast;744   assign tresp_tdata  = (VALIDATION_FEATURES) ? val_tresp_tdata  : axis_tresp_tdata;745   assign tresp_tkeep  = (VALIDATION_FEATURES) ? val_tresp_tkeep  : axis_tresp_tkeep;746   assign tresp_tuser  = (VALIDATION_FEATURES) ? val_tresp_tuser  : axis_tresp_tuser;747 748   assign axis_tresp_tready = (!VALIDATION_FEATURES) && tresp_tready;749   assign val_tresp_tready  = (VALIDATION_FEATURES)  && tresp_tready;750 751 752   // When enabled, report results.753   // This is a simulation-only option and cannot be synthesized754   generate if (SIM_VERBOSE) begin: tresp_reporting_gen755    srio_report756      #(.VERBOSITY              (2),757        .DIRECTION              (1),758        .NAME                   (8))  // Data is flowing into the core759      srio_tresp_report_inst760       (761       .log_clk                 (log_clk),762       .log_rst                 (log_rst),763 764       .tvalid                  (tresp_tvalid),765       .tready                  (tresp_tready),766       .tlast                   (tresp_tlast),767       .tdata                   (tresp_tdata),768       .tkeep                   (tresp_tkeep),769       .tuser                   (tresp_tuser)770      );771   end772   endgenerate773   // }}} End of TRESP Interface -------------------774 775 776   // {   {   { Target Generator/Checker -----------------777 778   // If internally-driven sequences are required779   generate if (VALIDATION_FEATURES) begin: tresp_validation_gen780    srio_response_gen_srio_gen2_0 srio_response_gen_inst (781       .log_clk                 (log_clk),782       .log_rst                 (log_rst),783 784       .deviceid                (deviceid),785       .source_id               (source_id),786       .id_override             (id_override),787 788       .val_tresp_tvalid        (val_tresp_tvalid),789       .val_tresp_tready        (val_tresp_tready),790       .val_tresp_tlast         (val_tresp_tlast),791       .val_tresp_tdata         (val_tresp_tdata),792       .val_tresp_tkeep         (val_tresp_tkeep),793       .val_tresp_tuser         (val_tresp_tuser),794 795       .val_treq_tvalid         (val_treq_tvalid),796       .val_treq_tready         (val_treq_tready),797       .val_treq_tlast          (val_treq_tlast),798       .val_treq_tdata          (val_treq_tdata),799       .val_treq_tkeep          (val_treq_tkeep),800       .val_treq_tuser          (val_treq_tuser)801      );802   end803   endgenerate804   // }}} End of Target Generator/Checker ----------805 806 807   // {   {   { TREQ Interface ---------------------------808   // Select between internally-driven sequences or user sequences809 810   assign treq_tready = (VALIDATION_FEATURES) ? val_treq_tready : axis_treq_tready;811 812   assign val_treq_tvalid  = (VALIDATION_FEATURES) && treq_tvalid;813   assign val_treq_tlast   = treq_tlast;814   assign val_treq_tdata   = treq_tdata;815   assign val_treq_tkeep   = treq_tkeep;816   assign val_treq_tuser   = treq_tuser;817 818   assign axis_treq_tvalid = (!VALIDATION_FEATURES) && treq_tvalid;819   assign axis_treq_tlast  = treq_tlast;820   assign axis_treq_tdata  = treq_tdata;821   assign axis_treq_tkeep  = treq_tkeep;822   assign axis_treq_tuser  = treq_tuser;823 824 825   // When enabled, report results.826   // This is a simulation-only option and cannot be synthesized827   generate if (SIM_VERBOSE) begin: treq_reporting_gen828    srio_report829      #(.VERBOSITY              (2),830        .DIRECTION              (0),831        .NAME                   (9))  // Data is flowing out of the core832      srio_treq_report_inst833       (834       .log_clk                 (log_clk),835       .log_rst                 (log_rst),836 837       .tvalid                  (treq_tvalid),838       .tready                  (treq_tready),839       .tlast                   (treq_tlast),840       .tdata                   (treq_tdata),841       .tkeep                   (treq_tkeep),842       .tuser                   (treq_tuser)843      );844   end845   endgenerate846   // }}} End of TREQ Interface --------------------847 848 849 850 851 852   // }}} End of Target-driven side ----------------853 854   // {   {   { Maintenance Interface --------------------855 856   // Select between internally-driven sequences or user sequences857   assign maintr_awvalid = (QUICK_STARTUP) ? val_maintr_awvalid : axis_maintr_awvalid;858   assign maintr_awaddr  = (QUICK_STARTUP) ? val_maintr_awaddr  : axis_maintr_awaddr;859   assign maintr_wvalid  = (QUICK_STARTUP) ? val_maintr_wvalid  : axis_maintr_wvalid;860   assign maintr_wdata   = (QUICK_STARTUP) ? val_maintr_wdata   : axis_maintr_wdata;861   assign maintr_bready  = (QUICK_STARTUP) ? val_maintr_bready  : axis_maintr_bready;862 863   assign maintr_arvalid = (QUICK_STARTUP) ? val_maintr_arvalid : axis_maintr_arvalid;864   assign maintr_araddr  = (QUICK_STARTUP) ? val_maintr_araddr  : axis_maintr_araddr;865   assign maintr_rready  = (QUICK_STARTUP) ? val_maintr_rready  : axis_maintr_rready;866 867 868   assign axis_maintr_awready = (!QUICK_STARTUP) && maintr_awready;869   assign axis_maintr_wready = (!QUICK_STARTUP) && maintr_wready;870   assign axis_maintr_bvalid = (!QUICK_STARTUP) && maintr_bvalid;871   assign axis_maintr_bresp = maintr_bresp;872 873   assign axis_maintr_arready = (!QUICK_STARTUP) && maintr_arready;874   assign axis_maintr_rvalid = (!QUICK_STARTUP) && maintr_rvalid;875   assign axis_maintr_rdata = maintr_rdata;876   assign axis_maintr_rresp = maintr_rresp;877 878   assign val_maintr_awready = (QUICK_STARTUP) && maintr_awready;879   assign val_maintr_wready = (QUICK_STARTUP) && maintr_wready;880   assign val_maintr_bvalid = (QUICK_STARTUP) && maintr_bvalid;881   assign val_maintr_bresp = maintr_bresp;882 883   assign val_maintr_arready = (QUICK_STARTUP) && maintr_arready;884   assign val_maintr_rvalid = (QUICK_STARTUP) && maintr_rvalid;885   assign val_maintr_rdata = maintr_rdata;886   assign val_maintr_rresp = maintr_rresp;887 888 889   // If internally-driven sequences are required890   generate if (QUICK_STARTUP) begin: quick_maint_gen891    srio_quick_start_srio_gen2_0 srio_quick_start_inst (892       .log_clk                 (log_clk),893       .log_rst                 (log_rst),894 895       .maintr_awvalid          (val_maintr_awvalid),896       .maintr_awready          (val_maintr_awready),897       .maintr_awaddr           (val_maintr_awaddr),898       .maintr_wvalid           (val_maintr_wvalid),899       .maintr_wready           (val_maintr_wready),900       .maintr_wdata            (val_maintr_wdata),901       .maintr_bvalid           (val_maintr_bvalid),902       .maintr_bready           (val_maintr_bready),903       .maintr_bresp            (val_maintr_bresp),904 905       .maintr_arvalid          (val_maintr_arvalid),906       .maintr_arready          (val_maintr_arready),907       .maintr_araddr           (val_maintr_araddr),908       .maintr_rvalid           (val_maintr_rvalid),909       .maintr_rready           (val_maintr_rready),910       .maintr_rdata            (val_maintr_rdata),911       .maintr_rresp            (val_maintr_rresp),912 913       // use these ports to peek/poke maintenance transactions914       .go                      (go_maint),915       .user_hop                (user_hop),916       .user_inst               (maint_inst),917       .user_addr               (user_addr),918       .user_data               (user_data[31:0]),919 920       .link_initialized        (link_initialized),921       .maint_done              (maint_done),922       .maint_autocheck_error   (maint_autocheck_error)923      );924   end else begin : no_quick_maint_gen925     assign maintr_awaddr         = 32'h0;926     assign maintr_wvalid         = 1'b0;927     assign maintr_wdata          = 32'h0;928     assign maintr_bready         = 1'b0;929     assign maintr_arvalid        = 1'b0;930     assign maintr_araddr         = 32'h0;931     assign maintr_rready         = 1'b0;932     assign maint_done            = 1'b1;933     assign maint_autocheck_error = 1'b0;934   end935   endgenerate936 937   // }}} End of Maintenance Interface -------------938 939 940   // {   {   { Statistics Gatherer ----------------------941 942   // When enabled, statistics gatherer collects details about performance.943   // This module is synthesizable and may be accessed through Chipscope944   generate if (STATISTICS_GATHERING) begin: stats_gen945    srio_statistics_srio_gen2_0 srio_statistics_inst (946       .log_clk                 (log_clk),947       .phy_clk                 (phy_clk),948       .gt_pcs_clk              (gt_pcs_clk),949       .log_rst                 (log_rst),950       .phy_rst                 (phy_rst),951 952       // outgoing port 1953       .tvalid_o1                  (ireq_tvalid),954       .tready_o1                  (ireq_tready),955       .tlast_o1                   (ireq_tlast),956       .tdata_o1                   (ireq_tdata),957 958       // outgoing port 2959       .tvalid_o2                  (iresp_tvalid),960       .tready_o2                  (iresp_tready),961       .tlast_o2                   (iresp_tlast),962       .tdata_o2                   (iresp_tdata),963 964       // incoming port 1965       .tvalid_i1                  (treq_tvalid),966       .tready_i1                  (treq_tready),967       .tlast_i1                   (treq_tlast),968       .tdata_i1                   (treq_tdata),969 970       // incoming port 2971       .tvalid_i2                  (tresp_tvalid),972       .tready_i2                  (tresp_tready),973       .tlast_i2                   (tresp_tlast),974       .tdata_i2                   (tresp_tdata),975 976       .link_initialized        (link_initialized),977       .phy_debug               (phy_debug),978       .gtrx_disperr_or         (gtrx_disperr_or),979       .gtrx_notintable_or      (gtrx_notintable_or),980 981       .register_reset          (register_reset),982       .reset_all_registers     (reset_all_registers),983       .stats_address           (stats_ad